sl74HC245 system logic semiconductor sls octal 3 - state noninverting bus transceiver high - performance silicon - gate cmos the sl 74HC245 is identical in pinout to the ls/als245. the d evice inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with ls/alsttl outputs. the sl 74HC245 is a 3 - state noninverting transceiver that is used for 2 - way asynchronous communication between data buses. the device has an active - low output enable pin, which is used to place the i/o ports into high - impedance states. the direction control determines whether data flows from a to b or from b to a. outputs directly interface to cmos, nmos, and ttl operating voltage range: 2.0 to 6.0 v low input current: 1.0 m a high noise immunity characteristic of cmos devices ordering information sl 74HC245n plastic sl 74HC245d soic t a = - 55 to 125 c for all packages pin assignment function table control inputs output enable direction operation l l data transmitted from bus b to bus a l h data transmitted from bus a to bus b h x buses isolated (high impedance state) x = don?t care logic diagram pin 20=v cc pin 10 = gnd
sl 74HC245 system logic semiconductor sls maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) - 0.5 to +7.0 v v in dc input voltage (refere nced to gnd) - 1.5 to v cc +1.5 v v out dc output voltage (referenced to gnd) - 0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 35 ma i cc dc supply current, v cc and gnd pins 75 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw tstg storage temperature - 65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol p arameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types - 55 +125 c t r , t f input rise and fall time (figure 1) v cc = 2.0 v v cc =4.5 v v cc =6.0 v 0 0 0 1000 500 400 ns this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maxi mum rated voltages to this high - impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused output s must be left open.
sl74 HC245 system logic semiconductor sls dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v 25 c to - 55 c 85 c 125 c unit v ih minimum high - level input voltage v out =0.1 v or v cc - 0.1 v i out 20 m a 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 v v il maximum low - level input voltage v out =0.1 v or v cc - 0.1 v i out 20 m a 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 v v oh minimum high - level output voltage v in =v ih or v il i out 20 m a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in =v ih or v il i out 6.0 ma i out 7.8 ma 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 v ol maximum low - level output voltage v in = v il or v ih i out 20 m a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v il or v ih i out 6.0 ma i out 7.8 ma 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 i in maximum input leakage current v in =v cc or gnd, pin 1 or 19 6.0 0.1 1.0 1.0 m a i oz maximum three - state leakage current output in high - impedance state v in = v i l or v ih v out =v cc or gnd, i/o pins 6.0 0.5 5.0 10 m a i cc maximum quiescent supply current (per package) v in =v cc or gnd i out =0 m a 6.0 4.0 40 160 m a
sl 74HC245 system logic semiconductor sls ac electrical characteristics (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to - 55 c 85 c 125 c unit t plh , t phl maximum propagation delay, a to b or b to a (figures 1 and 3) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns t plz , t phz maximum propagation delay , direction or output enable to a or b (figures 2 and 4) 2.0 4.5 6 .0 110 22 19 140 28 24 165 33 28 ns t pzl , t pzh maximum propagation delay , direction or output enable to a or b (figures 2 and 4) 2.0 4.5 6.0 110 22 19 140 28 24 165 33 28 ns t tlh , t thl maximum output transition time, any output (figures 1 and 3) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns c in maximum input capacitance (pin 1 or pin 19) - 10 10 10 pf c out maximum three - state i/o capacitance (i/o in high - impedance state) - 15 15 15 pf power dissipation capacitance (per transceiver channel) typical @25 c,v cc =5.0 v c pd used to determine the no - load dynamic power consumption: p d =c pd v cc 2 f+i cc v cc 40 pf figure 1. switching waveforms figure 2. switching waveforms
sl74 HC245 system logic semiconductor sls figure 3. test circuit figure 4. test circuit expanded logic diagram
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